More on: TI’s unique 10MHz dc-dc topology

Texas Instruments has unveiled a dc-dc topology, for which it is claiming industry’s highest current density: 50A/cm3, for a 12V 10A 10MHz converter.

More on: TI's unique 10MHz dc-dc topology

The target was to shrink a high-current dc-dc converter; and the best known path to small size is to increase switching frequency to reduce the need for large inductors and capacitors.

However, the standard buck converter is a hard-switched topology, which means that its mosfets are both passing current and have a voltage across them as they turn on or off.

As turn-off and turn-on are not instantaneous, for a few tens of nanoseconds during each transition the mosfets act like resistors. This causes small but finite ohmic losses. Higher frequency operation means more transitions and therefore more losses, and at something like 1MHz (with silicon mosfets) these ohmic switching losses become a significant chunk of total losses.

TI has been working on a topology that allows most of its mosfets to operate at half the input voltage, more than halving switching losses, TI energy systems engineer Pradeep Shenoy told Electronics Weekly. “The topology was found in research literature and transferred to the Kilby Labs,” he said. “Our team spent two years developing technologies to make it work in practice.”

Why not go resonant – and switch the mosfets at zero current or zero voltage? “Resonant converters have their own challenges,” said Shenoy. “It would be interesting if you could achieve full zero-voltage switching at 10MHz”.

The work has allowed a chip to be made, the TPS54A20, which can switch at up to 5MHz per phase without special magnetics or compound semiconductors, and can be used to deliver 10A from 8-14V inputs.

TI voltage & currentHow it works

The circuit is much like a two-phase buck converter (see diagram). In fact, from the synchronous rectifiers (Q1 and Q2) onward, it is exactly a two-phase buck converter, timed at 180°.

Now, while getting to grips with the scheme, it helps to know that the energy transfer capacitor (Ct) is large, so its voltage hardly changes through the cycle (<150mV ripple in the example).

It also helps to know that, due to the way the converter works, the voltage across Ct trends to half the input voltage and then stays there, so it is almost entirely accurate to think of Ct as a flying voltage source equivalent to Vin/2.

TI period 1During period 1 (see the timing diagram), energy enters the system as current through Q4, passing through Ct and L1 into the load. Because of inductor L, this current ramps upwards. As the input voltage is 12V, and Ct is charged to 6V, Q1’s drain has 6V on it during this phase. At the same time Q2 is on, allowing previously stored energy in L2 to transfer into the load, so the current in L2 is ramping down.

TI period 2&4In period 2, Q4 turns off leaving Ct open-circuit and doing nothing, while Q1 turns on and connects L1 to 0V, allowing it to start delivering energy from its field into the load. Meanwhile, L2 continues to feed energy into the load, its current continuing to diminish.

TI period 3Period 3 is the one unique to TI’s topology. Q2 opens, un-grounding the input end of L2, while Q3 closes connecting Ct to L2. Because the other end of Ct is still grounded by Q1, the capacitor (charged to Vin/2) pushes rising current into L2 – Essentially, Q2, Q3 and L2 have become a conventional buck converter fed with 6V) from the capacitor. Over at the top of the diagram, L1 continues to discharge its current into the load.

TI period 2&4Current flow in period 4 is in the same as period 2, except now L1 is delivering the last of its field to the load and, initiated by the opening of Q3 and closing of Q2, L2 has just started transferring its energy to the load. Ct is once more open-circuit, awaiting a charge top-up in the next period, which is a repetition of period 1.

Throughout this, Q1, Q2 and Q3 have only been exposed to Vin/2 (7V max) in the TPS54A20 – reducing switching losses and allowing the transistors to be optimised to work at this lower voltage. Only Q4 has to block the whole of Vin.

Efficiency is up to 92% delivering 3A at 1.8V, when switching at 2MHz/phase using a pair of 1210 (3.2 x 2.5 x 1.2mm) chip inductors. And it is still 85% when the load gets to 10A.

TI TPS54A20 photo500KHz switcher (left) occupies 1,270mm3 of which 232mm3 is inductor. Equivalents for the multi-MHz version are 157mm3 and, for the inductors (bottom right), 19.2mm3.

There is a lot going on beneath the surface in this converter. For example, one design details is a one-off mode that pre-charges Ct to half Vin at power-up before switching begins in earnest. Type ‘Shenoy patent’ into your favourite search engine to learn more.

“There are some unique things we are doing to make it all work,” he said and, despite all the optimisation, he assures: “this converter can safely operate without any problems from all voltages in the data sheet”.

Away from the core topology, there are some other design features to note.

As one of the target uses is high ratio conversion – 12V in 1.8V out, for example, high-side mosfet on-time can be a real limiting factor.

The team has achieved 14ns minimum on-time, allowing 14V in, 0.5V out operation at 5MHz/phase. Nominal on-time is set by an external resistor.

“We made a unique controller to enable this on-time,” said Shenoy.

Unusually for a fixed on-time topology, the converter can be synchronised to an external clock.

How does this work without breaking the laws of time?

It transpires that within the controller there is a fast inner constant on-time loop.

Around this, a slower outer loop – based on a phase-locked loop – gradually alters on-time to lock operational frequency to the external reference.

“If you have fast-changing load, it will spit-out more current pulses, then slow adaption will get you back to synchronised frequency,” said Shenoy. “For slowly changing loads, the PLL will keep up.”

Picking a capacitor

Having a capacitor in series with the energy loop in a dc-dc converter is not something anyone should be concerned about – SEPIC and Cuk converters have had them for a long time.

“We are using a regular MLCCs [multi-layer ceramic capacitors] – a couple of µF,” said Shenoy. “You have to take into account the nominal things when using a ceramic cap,” which are:

Temperature rating – X7R is suggested, and 125°C capability.

Calculate capacitance from voltage ripple and current

De-rate for voltage-dependant capacitance – some ceramics have 20%, some have 60-80%

Check self-heating from I(sub)RMS current

Magnetics

The inductor is often the tallest component in a dc-dc converter, and one of the design challenges was to reduce overall converter height by allowing the use of chip inductors.

“We use standard metal alloy chip inductors – 1.2mm high 1210’s for 2MHz/phase,” said Shenoy. “1.2mm height enables the converter to go on the back of circuit boards, for example DIMM modules.”

Iron dust? “Ferrite does have lower core loss but, if you manage your ripple, iron powder is no trouble at all,” said Shenoy, pointing out the efficiency figures above come from chip inductors. “One problem was finding low enough inductance, like around 100nH, so we worked with manufacturers to make inductors with fewer turns of wire.”

Closed-path inductors are specified, so the two inductors can be placed side-by-side (see photo).

The chip data sheet has selection guidance for inductors and capacitors as well as formulae and list of tested components. There is a host of other literature, an evaluation board, and support from the firm’s Webench tool. For links to most of this, click here.

TI is not claiming its topology is perfect, and points out its 50% duty cycle limitation, which in theory limits Vin min to 4x Vout (5x Vout, in practice, said the firm), and there is no option to shed a phase at low power.

 


Comments

One comment

  1. I am specializing in Power Electronics and my target is to work with solar energy and vehicle industry.All kinds of DC-DC, DC-AC are interesting for me.

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