Building an FPGA FIFO without using logic recourses

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of implementation of these designs are greatly enhanced by the feature-rich embedded elements present in the target technology. While simple FPGAs offer the ability to implement only basic logic functions, more advanced FPGAs provide embedded RAMs, multipliers, and highly specialized IO structures. These embedded elements are building blocks that – when combined with surrounding logic – can turn an embedded RAM into a FIFO, or an embedded multiplier into a finite impulse response (FIR) filter.

Thus, to expand upon these embedded building blocks to create more advanced functions, extra logic must typically be utilized and configured by the designer. This extra logic, in most cases, must be created, verified, implemented, and properly connected to the embedded elements by the designer in the source RTL.

But, what if this weren't the case? What if a designer could simply configure, for example, a highly flexible embedded RAM block in an FPGA to be a FIFO? And, what if this FIFO could have various depths and widths, have programmable output flags, and simultaneously operate in two separate clock domains – all without consuming any additional FPGA logic? Finally, what if this could be done without writing one line of RTL code? All of this is now possible using QuickLogic's new PolarPro line of low-power FPGAs. This paper will discuss how to use the PolarPro device – along with its associated design software, QuickWorks – to build these highly flexible FIFOs without using any of the FPGA's logic resources.

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