At the 2016 IEEE International Electron Devices (IEDM) Conference in San Francisco several exciting developments were presented that may change the way we keep information in consumer as well as business applications and devices. Although planar (2D) flash memory less than 10 nm appears to be off the table, other electronic devices were discussed with 7 nm features (especially FinFETs) and there was even a mention or two of 5 nm features. Let’s look at developments in NAND as well as emerging memory technologies, such as MRAM and even DRAM.
In a plenary talk Seok-Hee Lee from SK Hynix spoke about technology scaling challenges and opportunities for memory devices. He said that single-thread CPU performance increases have slowed since 2005 and the cache speeds available for compute cores have been stagnant. As a result the overall delay of computing devices hasn’t improved much recently. He indicated that evolution by itself will not be enough for the future and that memory technology needed to take two revolutionary paths. One of these paths focuses on high bandwidth memory and the other on high capacity memory, increasing the complexity of the conventional memory/storage hierarchy.
Below 15 nm 2D flash scaling is about done and we must depend upon 3D NAND for continued NAND flash advances. 3D NAND needs more efficient cell arrays to reduce the height as cell stacks achieve 100’s of layers. He discussed a concept called Z-scaling to reduce the overall stack height and enabling 356 cell layers. He also discussed the need to include peripheral electronics under the cells to allow more die per wafer. Quad-level cells to increase per cell bit density are another important development. Overall he expected 256 layer NAND flash within 5 years.
Things are moving fast in MRAM. Earlier in 2016, Everspin announced that they would have 1 Gb STT-MRAM chips before the end of 2016. In early November the company had these products on display. Everspin also introduced a 1 GB DDR3 compatible module based upon its 256 Mb DDR3 (perpendicular magnetic tunnel juniction) pMTJ STT-MRAM that it is shipping to selected customers.
In late October start-up MRAM company, Avalanche, said that it will start volume pMTJ STT-MRAM production in early 2017. While Everspin is working with manufacturing partner, Global Foundries, Avalanche is working with Sony Semiconductor Manufacturing Corporation (SSMC).
There were several sessions at the IEDM conference with MRAM papers. Among the papers there was a paper by SK Hynix and Toshiba on a 4 Gb STT-MRAM with a compact cell structure. There was also a paper from Everspin discussing the endurance and reliability of Spin-Torque MRAM products (it looks pretty good).
There was a poster session at the IEDM organized by the IEEE Magnetics Society with several interesting presentations on both MRAM storage devices as well as spin-based computing technologies (often called spintronics). Among the interesting demonstrations in this poster session was Samsung’s use of 8Mb STT-MRAM combined with SRAM as a frame buffer in a video display system.
In addition to papers by universities and memory companies, companies that make the equipment for creating MRAM, such as Singulus, also had displays. Many other major semiconductor manufacturers had MRAM posters including Toshiba and IBM.
Other emerging memory technologies were discuss at the IEDM. These included phase change memory (PCM), Resistive RAM (RRAM) and ferroelectric (and anti-ferroelectric) memories. A team from Stanford was able to do accurate measurements of temperature required to form or break the filaments in the target RRAM. They found that their RRAMs would switch at temperatures less than 260 F, less than the usual temperature generated in an MRAM. If this works in a functioning RRAM it means they can operate at lower temperature and thus use less energy.
Another group from Stanford and Berkeley was using a 3D vertically oriented RRAM device to create a hyperdimensional computing environment that could recognize words in 21 languages.
Ferro-electric devices were discussed in a few papers. A interesting papers from researchers in Germany discussed how common materials used in manufacturing DRAM today could be used to create a non-volatile DRAM. It turns out that a ZrO2 layer commonly used is an anti-ferroelectric. By changing the internal bias in the DRAM two stable non-volatile states can be created in the anti-ferroelectric layer. These states can be used to make a non-volatile version of DRAM. This would be a very interesting angle on a very mature process, and if it could be scaled successfully, would give some of the emerging memories a run for their money.
Engineers are clever creatures. It is fascinating how the various materials and complex structures in modern electronic devices continue to offer ripe opportunities for new discoveries and new methods for manufacturing. Based upon the presentations and discussions at the 2016 IEEE IEDM conference, we should have many more years of amazing technology development ahead of us.
