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  1. We present a chip-level area router for modern VLSI technolo-gies. The gridless area router can handle any number of layers, as well as rectilinear blockage areas on any layer. A two-stage divide-and-conquer strategy is applied so that the area router can handle very large chips. The first stage includes an area-minimiza-tion loop by using an effic... See more

    Detailed switch-box routing

    Figure 2: Flow of our routing system To solve the routing problem for block-based circuits, we … See more

    ACM Digital Library
    2. GLOBAL ROUTING/AREA MINIMIZATION

    Our area routing algorithm can be divided into two stages ---global routing and detailed routing. For the global routing, we extended the global router introduced in [1]. The global … See more

    ACM Digital Library
    2.1. Routing architecture

    A brief review of the routing architecture is presented here. Given a placement of macro cells (or building blocks), the chip area is divided into small regions by cut lines which … See more

    ACM Digital Library
    2.2. Chip size estimate

    The global router uses two directed graphs to accurately estimate the chip size. The chip’s height and width are calculated the same way. We use the calculation for the chip’s heig… See more

    ACM Digital Library
    2.3. Area minimization routing

    To minimize the chip area, we try to reduce the height and the width of the chip sequentially. The size of the chip is decided by the longest paths in the height and width graph. The … See more

    ACM Digital Library
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    Content
    Detailed switch-box routing
    2. GLOBAL ROUTING/AREA MINIMIZATION
    2.1. Routing architecture
    2.2. Chip size estimate
    2.3. Area minimization routing
    How do you get the final routing of a chip?
     
  1. ResearchGate
    https://www.researchgate.net/publication/220915618...

    (PDF) Chip-level area routing - ResearchGate

  2. ACM Digital Library
    https://dl.acm.org/doi/10.1145/274535.274564

    Chip-level area routing | Proceedings of the 1998 international ...

  3. CECS Department of UC Irvine
    https://www.cecs.uci.edu/~papers/iccad08/PDFs/Papers/07A.4.pdf
    [PDF]

    Area-I/O Flip-Chip Routing for Chip-Package Co-design - CECS

  4. Semantic Scholar
    https://www.semanticscholar.org/paper/Chi…

    [PDF] Chip-level area routing - Semantic Scholar

    WEBApr 1, 1998 — We present a chip-level area router for modern VLSI technologies. The gridless area router can handle any number of layers, as well as rectilinear blockage areas on any layer. A two-stage divide-and …

  5. Academia.edu
    https://www.academia.edu/.../Chip_level_area_routing

    (PDF) Chip-level area routing | Carl Sechen

    WEBA divide-and-conquer strategy is applied so that the area router can perform routing on a very large chip area. The first stage includes an area-minimization loop by using an efficient and accurate multi-layer global …

  6. People also ask
    What is a chip-level area router?
    A chip-level area router for modern VLSI technologies that can handle any number of layers, as well as rectilinear blockage areas on any layer, using a two-stage divide-and-conquer strategy. We present a chip-level area router for modern VLSI technologies.

    [PDF] Chip-level area routing | Semantic Scholar

    semanticscholar.org
    Can a chip-level area router handle rectilinear blockage?
    We present a chip-level area router for modern VLSI technolo-gies. The gridless area router can handle any number of layers, as well as rectilinear blockage areas on any layer. A two-stage divide-and-conquer strategy is applied so that the area router can handle very large chips.

    CHIP-LEVEL AREA ROUTING - ACM Digital Library

    dl.acm.org
    How do you get the final routing of a chip?
    The final routing of an entire chip is obtained by merging the results of all the switchboxes. The rest of the paper is organized as follows. Section 2 explains our global routing architecture and how we minimize the chip area. Section 3 describes the interface between global routing and detailed routing.

    CHIP-LEVEL AREA ROUTING - ACM Digital Library

    dl.acm.org
    How does a chip placement change affect the global routing results?
    In addition, to reduce the chip area, the placement has to change according to the routing results. The placement change may affect the global routing. The original global routing results may lose some accuracy. From the above analysis, an iterative process is apparently needed for solving the problem.

    CHIP-LEVEL AREA ROUTING - ACM Digital Library

    dl.acm.org
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  7. ResearchGate
    https://www.researchgate.net/publication/221340056...

    (PDF) Multi-layer chip-level global routing using an efficientgraph ...

  8. ACM Digital Library
    https://dlnext.acm.org/doi/abs/10.1109/12.368006

    Routing in a Three-Dimensional Chip - IEEE Transactions on …

  9. Semantic Scholar
    https://www.semanticscholar.org/paper/Chip-level...

    Figure 11 from Chip-level area routing - Semantic Scholar

  10. ntu.edu.tw
    http://cc.ee.ntu.edu.tw/~ywchang/Papers/dac09-flip-chip.pdf
    [PDF]

    Flip-Chip Routing with Unified Area-I/O Pad Assignments for …

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