What If We Had Bi-Directional RRAM?

SET, RESET and the ideal memristor for neuromorphic computing.

popularity

The ideal memristor device for neuromorphic computing would have linear and symmetric resistance behavior. Resistance would both increase and decrease gradually, allowing a direct correlation between the number of programming pulses and the resistance value. Real world RRAM devices, however, generally do not have these characteristics. In filamentary RRAM devices, the RESET operation can raise resistance gradually, but the SET operation to create the low resistance state tends to be abrupt. Several proposed artificial synapse designs accommodate this behavior by using two or more memristors per synapse. For example, with two RRAMs connected in opposite directions, a pulse that increases the resistance of one will decrease the resistance of the other, allowing the synapse as a whole to make a symmetric transition. This solution works, but increases design complexity and expands the required circuit area. Device manufacturers would like to be able to modify the device structure to achieve more ideal behavior.

One research group, a collaboration between Beijing’s Tsinghua University and Arizona State University (Tempe, AZ), observed that the abrupt SET transition in filamentary RRAMs is due to the formation of a single, strong conductive filament. More precisely, oxygen vacancies in the oxide layer of a TiN/HfOx/TiN stack move in response to an applied electric field. A single conductive filament implies that those vacancies are tightly correlated around a narrow region, while a more random distribution of vacancies would be expected to lead to formation of multiple weak conduction paths. At December’s IEEE Electron Device Meeting, Bin Gao and colleagues proposed a vacancy order parameter, Ov, where 0 is a completely random vacancy distribution and 1 is an abrupt, nonlinear distribution. Below a critical region when Ov is between 0.25 and 0.3, a gradual resistance transition occurs.

To investigate filament growth behavior, the researchers compared devices with a metal cap layer to devices with a “thermal enhanced layer” intended to reduce thermal conductivity. In the devices with a metal cap layer, the applied electric field dominated oxygen vacancy formation. Once the first vacancies formed, perhaps at defects or similar locations, new vacancies tended to form near them, ultimately resulting in a single conductive filament.

In contrast, in devices with the thermal cap layer, the overall device temperature increased. The higher temperature was associated with higher rates of vacancy formation throughout the device, and therefore a more uniform distribution of vacancies. Under the influence of an electric field, these vacancies formed multiple percolation paths, leading to numerous weak conductive filaments. These filaments both formed and dissolved at lower applied voltages, offering more gradual SET and RESET behavior. Doping with aluminum appeared to localize vacancy formation near the dopant sites, again contributing to a low order parameter and weak filament formation.

With multiple weak filaments rather than a single strong filament, the group was able to create artificial synapses with more gradual resistance change during both SET and RESET processes. Testing with a three-layer perceptron network with 158,800 synapses, they found that increasing the number of pulses between the minimum and maximum resistance values improved digit recognition accuracy. Larger resistance fluctuations degraded accuracy. Though the addition of a cap layer does increase process complexity, the reduced design complexity and circuit area appear to justify the effort.

Related Stories
What’s Next In Neuromorphic Computing
Why commercialization will require improvements in devices and architectures.
New Memories And Architectures Ahead
So far there is not widespread adoption, but many see change as inevitable.
What Happened To ReRAM?
After years of delays, this next-gen memory is finally gaining traction.
Power/Performance Bits: July 11’17
Prototype 3D chip that integrates computation and data storage, based on carbon nanotubes and resistive RAM (RRAM) cells.



Leave a Reply


(Note: This name will be displayed publicly)